A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches

This paper presents the design and prototype of an intelligent, 3-Dimensional-Queue (3DQ) for highperformance, scalable, input bu ered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and eliminates Head-Of-Line (HOL) blocking. Using FieldProgrammable-Gate-Array (FPGA) devices, our prototype hardware can process ATM cells at 622 Mb/s (OC12). Using more aggressive technology (Multi-ChipModule (MCM) and fast GaAs logic), the same 3DQ design can process cells at 2.5 Gb/s (OC-48). Using 3DQ and Matrix-Unit-Cell-Scheduler (MUCS) as essential components, an input-bu ered ATM switch system has been designed, which can achieve near-100% link bandwidth utilization.